MVME1X2P4 boards use SDRAM (Synchronous DRAM) in place of DRAM. The MVME162P4’s 16/32MB shared SDRAM is configurable to emulate either of the following memory models:
1. 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
2. 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM
The two memory controllers modeled in the Petra ASIC duplicate the functionality of the “parity memory controller” found in MC2 ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs. Board firmware will initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will enable the parity (MC2) memory controller model. If the Petra ASIC is supporting MVME1X2P2 functionality, firmware will enable either the parity or the MCECC memory controller model, depending on the board configuration. Board configuration is a function of switch settings and resistor population options.
S6 comes into play in the MCECC memory controller model. S6 is a four-segment slide switch whose lower three segments establish the size of the ECC DRAM (segment 4 is not used.) Refer to the illustration and table below for specifics.
Note: For the MCECC memory model to be enabled, the MC2 emulation must be disabled. You disable the MC2 memory model by setting the MC2 DRAM size select switch (S3) to 110 (Off/Off/On). Refer to MC2 DRAM Size (S3) for further details.
The factory default setting for S6 is 16MB (On/Off/On). If you modify the switch settings, you will need to execute env;d so that the firmware recognizes the new memory defaults.
Note: Model Number: MVME162P-344SE, Characteristics: 32MHz 68040, 16MB SDRAM, 2 SIO, 4 DMA IP, SCSI/Ethernet is used on Universal UIC HSP4797L Hitachi Sanyo TCM-X100 P.C.B. Mount 6300901030